Penerangan: UNIV AT6000 PHYSICAL DESIGN SYS
Penerangan: UNIVER DESIGN SYS VWDRAW/VIEWSIM
Penerangan: INTEGRAPH SCHEM SYNTH/SIM MAINT
Penerangan: ATMEL SYNARIO VHDL SYNTHESIS OPT
Penerangan: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Penerangan: MENTOR V8 LIBRARIES/INTRFC MAINT
Penerangan: ATMEL SYNARIO VERILOG SIM OPTION
Penerangan: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Penerangan: MENTOR V8 LIBRARIES/INTERFACE
Penerangan: SYNOPSYS LIBRARIES/INTRFC MAINT
Penerangan: PRO CHIP SOFTWARE LICENSE
Penerangan: ATMEL SYNARIO VHDL SYNTHESIS OPT
Penerangan: FPGA DESIGN SYS W/VWDRAW/VIEWSIM
Penerangan: FPGA VIEWLOGIC-BASED INTRMED UPG
Penerangan: FPGA DESIGN SYSTEM W/VIEWDRAW
Penerangan: CADENCE LIRARIES/INTRFC MAINT
Penerangan: CADENCE VERILOG LIB/INTRFC MAINT
Penerangan: SYNOPSYS LIBRARIES/INTRFC MAINT